Embodiments of the present invention relate to a method for adjusting a clock frequency of an oscillator and to an oscillator clock frequency adjusting circuit. In particular, embodiments of the invention relate to a method for automatically adjusting the clock frequency of a Universal Serial Bus (USB) device and to a USB device including such a clock frequency adjusting circuit.
Universal Serial Bus relies on a technical specification detailing communications between a host controller (such as a personal computer) and a device, such as a keyboard, mouse, digital camera, external memory, or the like via an interface called a USB port. The USB Specification 2.0 defines different data transfer rates, including a low-speed mode at 1.5 Mb/sec with an accuracy margin of ±1.5%.
As the host controller does not send a clock signal to the device, the device must generate its own clock signal with sufficient precision to meet the required USB data transfer rate. A quartz crystal oscillator may be provided, but this solution is unsuitable for low-cost applications and occupies too much area. An alternative is to base the generation of clock cycles on a synchronization signal sent by the host, such as a Start of Frame or a “Keep Alive” signal sent in the absence of traffic to keep the device from entering a suspended state. In these cases, a time frame between two consecutive synchronization signals is 1 ms. For a USB device operating with a clock frequency of 6000 KHz, an accuracy margin of +1.5% provides for a frequency margin of +90 KHz, resulting in between 5910 and 6090 clock cycles per 1 ms time frame.
FIG. 1 shows a clock frequency adjusting circuit 1 including an oscillator 2 and a calibration unit 3. The oscillator 2 generates a clock signal CLK which is fed back to the calibration unit 3. When the calibration unit 3 receives a first instance of a synchronization signal SNC, it begins counting the number of cycles of the clock signal CLK on its input until the next instance of the synchronization signal, when it stops counting. The calibration unit 3 determines the difference between the counted number of cycles and the desired number of cycles, then supplies a control signal S to the oscillator 3, which increases or decreases its frequency accordingly.
At this point, the “frequency step” of the oscillator, the change in frequency on output of oscillator 2 due to the application of the control signal S, is unknown. This is because the operation of the oscillator may vary over time, such as due to an increase in temperature, altering the operation of the oscillator. Thus, the desired frequency will typically be under- or over-shot after the first adjustment phase.
The number of clock cycles is therefore again counted during the next time frame to determine the frequency step of the oscillator. The calibration unit 3 again supplies control signal S to the oscillator 3 to obtain the desired frequency after the second time frame.
It may therefore be desired to provide a circuit able to adjust the frequency of an oscillator after a single time frame.